1. Field of the Invention
The present invention relates to a fabrication method of a nonvolatile semiconductor memory device and more particularly, to a fabrication method of a flash Electrically Erasable Programmable Read-Only Memory (EEPROM) with the split-gate type memory cells.
2. Description of the Prior Art
A nonvolatile semiconductor memory device is one that retains its stored data even while power is off. Though several types of such devices have been developed, an Electrically Programmable ROM (EPROM) and a flash EEPROM are suitable for large-scale integration because their memory cell structures are advantageous to reduction in size.
The flash EEPROM can both electrically write or store data therein and electrically erase its stored data (in a specified area in a flash). Therefore, recently, the flash EEPROM has been attracting a great deal of attention because it will possibly replace magnetic memory devices in the future.
Stacked-gate and split-gate types are typically used in the memory cell structures of the flash EEPROM that have been developed.
Since the stacked-gate type memory cell structure is the same as the standard memory cell structure of the EPROM, it is advantageous for size-reduction. However, there is a disadvantage that the operational characteristics of the flash EEPROM deteriorate during an erase operation due to the overerase phenomenon.
On the other hand, the split-gate type memory cell structure, is advantageous in that the overerase phenomenon causes no problem in practical use.
FIGS. 1, 2A and 2B show a conventional split-gate type flash EEPROM, which is disclosed in ISSCC Digest of Technical Papers, 1989, pp 138, 139 and 316.
As shown in FIG. 1, on a P-type silicon substrate 201, a patterned field oxide film 202 formed to produce active regions by a local oxidation of silicon (LOCOS) method. A plurality of N.sup.+ -type source regions 208B with strip-like plane shapes are arranged in the active regions, respectively.
The drain regions 208A are placed in X and Y directions perpendicular to each other at regular intervals to form a matrix array, respectively.
The source regions 208B extend along the X direction and are placed in the Y direction at regular intervals. Each of the drain regions 208A is disposed between adjacent two ones of the source regions 208B in the Y direction. As shown in FIG. 1, one of the drain regions 208A and adjacent one of the source regions 208B form one memory cell. Each of the drain regions 208A is used in common by two ones of the memory cells adjacent to each other in the Y direction.
Each of the memory cells has a channel area CA with a rectangular plane shape between corresponding one of the drain regions 208A and corresponding one of the source regions 208B. The length of the channel area CA along the Y direction is nearly equal to the sum of gate lengths of a floating gate and a control gate, i.e., (.div.Fa3+Sa3) or (.div.Fa3+Sa3). The width of the channel area CA along the X direction is equal to a gate width W.
As shown in FIG. 1, each of the drain regions 208A has two ones of the channel areas CA placed at each side thereof in the Y direction.
The conventional flash EEPROM has a plurality of the memory cell pairs shown in FIG. 1. However, since these pairs are the same in configuration and function as each other, only one of the pairs will be described below for the sake of simplification of description.
Here, one cell of the memory cell pair at the left side in FIG. 2B is called a "first memory cell" and the other at the right side is called a "second memory cell".
With the first and second memory cells, as shown in FIG. 2B, first gate insulator films 204a and 204b with the same thickness of d.sub.0 are selectively formed on the uncovered surface of the substrate 201 to cover drain-side parts thereof in the channel areas CA, respectively. These first gate insulator films 204a and 204b are made of silicon dioxide produced by thermal oxidation or the like. The drain-side ends of the gate insulator films 204a and 204b cover the source-side ends of the drain region 208A also, respectively. The lengths of the films 204a and 204b in the Y direction are nearly equal to Fa3 and Fb3, respectively.
Floating gate electrodes 215a and 215b, which are made of a first conductor such as polysilicon, are formed on the first gate insulator films 204a and 204b, respectively. The gate lengths Fa3 and Fb3 of the gate electrodes 215a and 215b are L.sub.1.
The gate electrodes 215a and 215b extend to the field oxide film 202 in the X direction at each side of the drain region 208A, as shown in FIG. 1.
The floating gate electrodes 215a and 215b have rectangular top faces and four vertical side faces almost perpendicular to the substrate 201, respectively.
Second gate insulator films 206a and 206b with the same thickness of d.sub.1 are selectively formed to cover the top faces of the floating gate electrodes 215a and 215b and the remaining uncovered surface of the substrate 201, respectively. The films 206a and 206b also cover the vertical side faces of the gate electrodes 215a and 215b except for their vertical side faces near the drain region 208A, respectively. These second gate insulator films 206a and 206b are made of silicon dioxide produced by thermal oxidation or the like.
The drain-side ends of the source regions 208B are also covered with the second gate insulator films 206a and 206b, respectively.
Control gate electrodes 217a and 217b are formed on the second gate insulator films 206a and 206b to cover the floating gate electrodes 215a and 215b, respectively. The gate electrodes 217a and 217b are made of a second conductor such as polysilicon.
The widths of the control gate electrodes 217a and 217b in the Y direction are equal to the sum of the gate lengths L.sub.1 and L.sub.2 of the floating gates 215a and 215b and the control gates 217a and 217b, i.e., (=Fa3+Sa3) and (=Fa3+Sa3), respectively.
The vertical side faces of the control gates 217a and 217b at their drain-side ends are aligned with the corresponding vertical side faces of the floating gate electrodes 215a and 215b, respectively.
Word lines extending along the X direction are made of the second conductor to be united with a corresponding control gate electrodes 217a and 217b, respectively.
An interlayer insulator film 209 provided over the entirety of the substrate 201 to cover the control gate electrodes 217a and 217b, the word lines and the uncovered field oxide film 202. Bit contact holes 210 are provided in the interlayer insulator film 209 at the positions right above the respective drain regions 208A.
Bit lines 211 are formed on the interlayer insulator film 209 to extend along the Y direction. The bit lines 211 are arranged at regular intervals in the X direction. Each of the bit lines 211 is connected to the corresponding drain regions 208A arranged along the Y direction.
The floating gate electrodes 215a and 215b are entirely surrounded by the first gate insulator films 204a and 204b, the second gate insulator films 206a and 206b, and the interlayer insulator film 209, respectively.
With the conventional split-gate type flash EEPROM, as stated above, the first and second memory cells contain metal-oxide-semiconductor (MOS) select transistors with the control gate electrodes 217a and 217b the gate lengths Sa3 and Sb3 of which are L.sub.2 and the gate widths of which are W, respectively.
Therefore, even if the overerase phenomenon occurs in any memory cell, no problem arises in a read operation for the other memory cells if the cell concerned is not selected by the corresponding select transistor.
As shown in FIGS. 1, 2A and 2B, the first and second memory cells also contain MOS storage transistors with the control gate electrodes 217a and 217b the gate lengths Fa3 and Fb3 of which are L.sub.1 and the gate widths of which are W, respectively.
The above conventional flash EEPROM has the following problems.
The first problem relates to data-storage. The above conventional split-gate type EEPROM exhibits inferior data-storage compared to a stacked-gate type one. The reason is as follows:
In the conventional stacked-gate type flash EEPROM, the control gate covers only two sides or edges of the corresponding floating gate with a parallelepiped shape on the field oxide film.
On the other hand, in the conventional split-gate type flash EEPROM described above, the control gate 217a and 217b covers five sides or edges of the corresponding floating gate 215a and 215b with a parallelepiped shape and two apexes or vertexes thereof on the field oxide film 202. Therefore, the EEPROM of this type has more positions in which an electric field easily concentrates than the stacked-gate type one, resulting in deteriorations of the data-storage characteristic.
The electric field tends to concentrate in the vertexes of the floating gate 215a and 215b especially.
The second problem relates to the fabrication method. This problem is that the data-writing periods of time of the first and second memory cells where the drain regions 208A is commonly used are different from each other. This is chiefly due to the gate length difference between the floating gates 215a and 215b.
The inventor fabricated the conventional split-gate type flash EEPROM and investigated its data-writing characteristic under the following conditions.
The doped-impurity concentration of the P-type substrate 201 was in the range of 10.sup.18 to 10.sup.17 cm.sup.-1. The first gate insulator films 204a and 204b were made of a patterned silicon dioxide film whose thickness d.sub.0 is 10 nm. The second gate insulator films 206a and 206b were also made of a patterned silicon dioxide film whose thickness d.sub.1 is 25 nm. The floating gate electrodes 215a and 215b were made of a patterned polysilicon film with a thickness of 150 nm. The floating gate electrodes 215a and 215b overlapped with the field oxide film 202 by 0.5 .mu.m width at both sides of the electrodes 215a and 215b, respectively. The gate lengths L.sub.1 of the floating gate electrodes 215a and 215b were 0.85 .mu.m in design value; however, the obtainable lengths L.sub.1 were in the range of 0.7 to 1.0 .mu.m since the tolerance of the positional alignment was .+-.0.15 .mu.m.
When a data value was written into the floating gate 215a of the first memory cell, a voltage V.sub.PP (for example, 12 V) was applied to the control gate electrode 217a and a voltage V.sub.CC (for example, 6 to 7 V) was applied to the drain region 208A through the corresponding bit line 211. At this time, control gate electrodes and bit lines corresponding to the other memory cells were retained at 0 V or grounded, and all source regions were also retained at 0 V including the source regions 208B of the first memory cell.
Therefore, a voltage V.sub.TM =V.sub.PP .times.]C.sub.21 /(C.sub.1 +C.sub.21)] was applied to the floating gate electrode 215a during the data write operation where C.sub.1 was a capacitance between the floating gate electrode 215a and the substrate 201, C.sub.21 was a capacitance between the floating gate electrode 215a and the control gate electrode 217a, and C.sub.22 was a capacitance between the control gate electrode 217a and the substrate 201.
For example, when Fa3=1.0 .mu.m in the first memory cell and Fb3=0.7 .mu.m in the second memory cell, the fluctuation of the voltage V.sub.TM from its design value was in the range of -1 to +2% approximately, which was acceptable.
However, the data writing period T.sub.W of time varied in a large range even if the other tolerances other than the positional alignment were neglected. For example, if the design value of the data writing period t.sub.W was defined as t.sub.WO, t.sub.W was in the range from 2.8 to 4.5.multidot.t.sub.WO in the first memory cell (L.sub.1 =Fa3=1.0 .mu.m) and t.sub.W was in the range from 0.7 to 0.75 t.sub.WO in the second memory cell (L.sub.1 =Fb3=0.7 .mu.m).